The present invention relates to a non-volatile memory device and, more particularly, to a method of manufacturing in which, the conductive layer for a floating gate is used to gap fill a shorted trench (i.e., the trench depth is smaller than in the conventional method), an insulating layer is then formed on the gap fill conductive layer to complete a formation of an isolation structure so that it is possible to prevent voids from being generated in the isolation structure.
In general, the shallow trench isolation (STI) method is used as an isolation forming method for isolating an active area from an isolation area in the non-volatile memory device. As a semiconductor device becomes more integrated, a critical dimension of the active area and a critical dimension of the isolation area (i.e., areas between the active areas for isolating the active areas from each other) are decreased due to a reduction of the design rule. Due to the above configuration, a trench is not completely filled with a high density plasma (HDP) oxide, and voids are generated in the HDP oxide. The above mentioned void may degrade the isolation characteristics of the semiconductor device and generate a cell to cell leakage current, reducing the reliability of the device.